library IEEE;
use IEEE.std_logic_1164.all;

entity DataOutput is
  Port (--External Signals
        --Data Signals
        DataOut : out std_logic_vector(15 downto 0);
        --Output Signals
        PCLK : out std_logic;
        ROW_CLK : out std_logic;
        HSYNC : out std_logic;
        VSYNC : out std_logic;
        --Input Signals
        RESET : in std_logic;
        PWDN : in std_logic;        
        --Control Signals
        I2C_DATA : inout std_logic;
        I2C_CLK : inout std_logic;
        --Misc. Signals
        MISCIO : out std_logic_vector(5 downto 0);
        
        --Internal Signals
        DataIn : in std_logic_vector(15 downto 0));
end DataOutput;

architecture behavioral of DataOutput is
  signal start,stop,addrMatch,addrCheck : std_logic:='0';
  signal address : std_logic_vector(6 downto 0):="1010101"; --7 bit address
  signal data : std_logic_vector(7 downto 0);
  signal bitCout : integer:=0;
begin
  
  idle: process(I2C_CLK, I2C_DATA)
  begin
    if I2C_CLK = '1' and I2C_DATA'event and I2C_DATA = '0' then
      start <= '1';
    end if;
  end process;
  
  recieve: process(start, I2C_CLK, I2C_DATA)
  begin
    
    
end behavioral;